1. Field of the Invention
The present invention is directed to application specific integrated circuit (ASIC) designs. More specifically, but without limitation thereto, the present invention is directed to identifying and correcting problems in RTL code for an ASIC design.
2. Description of the Prior Art
Previous approaches to correcting design defects in application specific integrated circuit (ASIC) designs require a significant amount of time analyzing the backend flow, or layout, of the ASIC design. Attempting to resolve design problems at this stage in the design typically increases turnaround time (TAT) and jeopardizes schedule commitments.